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60210hkim vl-2635 no.a1696-1/23 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LC823410-10R overview the LC823410-10R is a system ic that uses ultra-low power consumption technology to realize long-time playback and recording, and has various ic recorder functions. the ic is optimal for use in ic recorder applications. features ? arm7tdmi-s tm * 1 , amba ? (ahb/apb) system -on-chip sram (160kbytes) -on-chip rom (256kbytes) -dma controller (2 channels) -interrupt controller (external 6 channels) -sio (2 channels), uart (3 channels, of whic h 2 channels run on the 12mhz oscillator xt1.) continued on next page. ordering number : ena1696 cmos ic ultra-low power consumption 7.0mw large-scale system lsi, goklow, for ic recorders *1: arm logo, arm powered logo and, arm7td mi are registered tradem ark of arm limited. supply of this product does not convey license nor imply any right to distribute content created with this product in revenue-generating broadcast syst ems (terrestrial, satellit e, cable and/or other distribution channels), streaming ap plications (via internet, intranet s and/or networks), other content distribution systems (pay-audio or audio-on-demand applications and the like) or on physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like). supply of this product does not convey license und er the relevant intellectual property of thomson and/or fraunhofer gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. an independent license for such use is required. for details, please visit http://mp3licensing.com/ .
LC823410-10R no.a1696-2/23 continued from preceding page. -i 2 c (1 channel, single master, full speed mode/standard mode support) -gpio (multiplexed port i/o pin, 32 channels) -plain timer, multiple timer (2 channels, runs on the 12mhz oscillator xt1) -10-bit a/d converter (4 channels) -nand flash memory i/f (multi-level cell nand) 4-bit correctable ecc, automatic correction of error bits -sd card i/f (cprm not supported) [optional] sd card clock can be generated through ahb clock. -memory stick i/f [optional] -usb2.0 device i/f with phy communication operation possible even when the ahb runs at a low clock rate. insertion/extraction detection possible even when the phy clock is stopped. -rtc (realtime clock) operation at a voltage independent from the internal core operating voltage, and rtc only power on operation possible. -jtag ice ? mp3 *2 hard-wired encoder/decoder -mpeg1, mpeg2, mpeg2.5 (fs=8khz to 48khz, 8kbps to 320kbps) ? high quality sound technologies & functions (underlined functions support 96khz sampling) -sanyo ?aviss? surround circuit -yy filter high frequency compensation circuit (2 modes, lp2: high bit rate and lp4: low bit rate) -sampling rate converter. convertible up to 96khz (max.) within the range of 0.5 to 64 times -6-band equalizer. equalizer characteristics can be ad justed by setting the coefficient. -digital volume and mute functions (except the recording system). both db and linear rate of change can be designated. -level meter (except the recording system) -audio timer function. lr clock count and interrupt generation function ? on-chip 16-bit pcm input/output in terface. master/slave mode, i 2 s support ? 12mhz oscillator xt1 + pll dedicated for audio enable audio clock generation also supports audio operations using 16.9344mhz oscillator xt2 (optional). ? supply voltages (typical) -logic, usb phy1, xtal, pll1, rtc = 1.1v (when no usb devices connected) or 1.5v (when usb devices connected) -i/o, adc, usb phy2, pll2 = 2.8v (when no usb devices connected) or 3.3v (when usb devices connected) specifications absolute maximum ratings at *v ss * = 0v parameter symbol conditions ratings unit v dd 1 v dd rtc v dd xt av dd phy1 av dd pll1 -0.3 to 1.8 v maximum supply voltage v dd 2 v dd 3 av dd adc av dd phy2 av dd pll2 -0.3 to 3.96 v v i -0.3 to *v dd *+0.3 (max3.96) v input voltage v iusb dp and dm pins -0.3 to 5.25 v operating ambient temperature topr -30 to +70 c storage ambient temperature tstg -55 to 125 c *2: mpeg layer-3 audio coding technology licensed from fraunhofer iis and thomson.
LC823410-10R no.a1696-3/23 allowable operating range at ta = -30 to +70 c low voltage operation high voltage operation parameter symbol conditions min typ max min typ max unit v dd 1 1.05 1.1 1.2 1.35 1.5 1.65 v v dd xt 1.05 1.1 1.2 1.35 1.5 1.65 v av dd pll1 1.05 1.1 1.2 1.35 1.5 1.65 v av dd pll2 2.7 2.8 3.3 2.7 2.8 3.6 v v dd rtc 0.9 1.1 1.65 0.9 1.5 1.65 v v dd 2 2.7 2.8 3.3 2.7 2.8 3.6 v 2.7 2.8 3.3 2.7 2.8 3.6 v v dd 3 1.7 1.8 1.95 1.7 1.8 1.95 v av dd adc 2.7 2.8 3.3 2.7 2.8 3.6 v av dd phy1 1.05(*1) 1.1 1.2 1.35 1.5 1.65 v supply voltage av dd phy2 2.7(*1) 2.8 3.3 3.0 3.3 3.6 v input voltage v in 0*v dd *0 *v dd *v ( * 1) in the low-voltage operation state, although transition from this state to the high-voltage operation state and operation after the transition are guaranteed, all operations are not guaranteed in the low-voltage state. ( * 2) the relations below are assumed in all operation states. ? v dd 1=v dd xt=av dd pll1=av dd phy1 ? av dd phy2>=av dd adc ? v dd 2>=av dd pll2 ? v dd 2>=v dd 3 where , ? v dd 1, v dd xt, and av dd hy1 have the same electrical potential b ecause they are connected within the ic. ? av dd pll1>=v dd 1 ? besides the above two points, voltage differences up to 0.1v are considered to be equal. also, during rtc-only operation, the above v dd rtc voltage can be applied at backupb = low input and application of v dd * = 0v except for v dd rtc. ( * 3) low-voltage operation: this is an operation st ate that enables low power consumption during music playback and other operations. high-voltage operation: this is an operati on state on the assumption that usb is used. low voltage operation high voltage operation parameter symbol function min typ max min typ max unit fxin1 arm & peripherals 12 12mhz 100p-pm (using usb) mhz fxinrtc rtc 32.768 32.768 khz fxin2 audio 16.9344 16.9344 mhz input oscillation frequency frc rc 0.4 1 2 0.4 1 2 mhz fahb arm ahb 0 30 0 60 mhz fapb arm apb 0 30 0 60 mhz internal operating frequency faud audio 0 16.9344 36.864 0 16.9344 36.864 mhz normal 19 24 mhz sd i/f clock frequency fsdclk high speed (v dd 3>=2.7v sddrv=1) 25 40 mhz parallel 30 30 mhz ms i/f clock frequency fsclk serial 20 20 mhz
LC823410-10R no.a1696-4/23 dc characteristic at ta = -30 to +70 c, v dd 2 = 2.7 to 3.6v, v dd rtc = 0.9 to 1.65v, v dd 3=1.7 to 1.95v, 2.7 to 3.6v ratings parameter symbol pins conditions min typ max unit (1) 0.7 v dd 2 v (2) schmitt 0.75 v dd 2 v input high level voltage v ih (3) 0.7 v dd rtc v (1) 0.3 v dd 2v (2) schmitt 0.25 v dd 2v input low level voltage v il (3) 0.2 v dd rtc v (4) i oh =-2ma v dd 2-0.4 v (5) i oh =-4ma v dd 3-0.34 v output high level voltage v oh (6) i oh =-0.3ma v dd rtc-0.3 v (4) i ol =2ma 0.4 v (5) i ol =4ma 0.34 v output low level voltage v ol (6) i ol =0.3ma 0.3 v output leakage current i oz (7) hi-z output -10 10 a pull-up resistor rup (8) 50 100 150 k pull-up resistor rup (9) 30 45 80 k pull-down resistor rdn (10) 40 70 160 k pull-down resistor rdn (11) 20 50 90 k (1) fd7-0, sdcmd, sdat3-0, bck, lrck, mclk, scl, sda, tioca1-0, sdi1, rxd2-0, sdo0, txd2-0, xfce1-0, phi, tck, tdi, tms, sdi0, din, sdcd, sdwp (2) test6-1, ntrst, nres, extint6-0, extfiq, sck1-0, xfbsy (3) backupb, vdet (4) sck1-0, fd7-0, exd15-0, bck, lrck, mclk, scl, sda, tioca1-0, sdi1, sdi0, rxd2-0, txd2-0, xfce1-0, phi, extfiq, extint4-0, dout, rtck, tdo, xale, xcle, xfre, xfwe, xfwp (5) sdclk, sdcmd, sdat3-0 (6) rtcint (7) sck1-0, fd7-0, sdcmd, sd at4-1, bck, lrck, mclk, scl, sda, tioca1-0, sdi1, rxd2-0, sdo1-0, txd2-0, xfce1-0, phi, extfiq, extint4-0, rtck, xale, xcle, xfre, xfwe, xfwp, rtcint (8) extfiq, sck1, sdo1, txd2-0, rxd2-0, tioca1-0, sdi1, extint4-0, xfce1-0, scl, sda, lrck, mclk, phi, sck0, sdi0, sdo0, tck, tdi, tms, ntrst ,xfwe, xfre, xale, xcle, xfwp (9) sdcmd, sdat3-0, sdcd (10) sdat3-0 (11) din, fd7-0 (caution) the following pins are not in cluded in dc characteristics. rref, dm, dp, vcnt1, vcnt2, an3-0, xin1, xin2, xin32k, xout1, xout2, xout32k
LC823410-10R no.a1696-5/23 pll1 characteristics at ta = -30 to +70 c av dd pll1=1.05 to 1.2v av dd pll1=1.35 to 1.65v parameter symbol conditions min typ max min typ max unit vco voltage vcnt1 0av dd pll1 0 av dd pll1 v vco maximum oscillation frequency fmax 90 180 mhz vco minimum oscillation frequency fmin 60 60 mhz phase comparison frequency fref 30 30 mhz pll lock time tlock 510 5 10ms pll2 characteristics at ta = -30 to +70 c, av dd pll2 = 2.7 to 3.6v ratings parameter symbol conditions min typ max unit vco voltage vcnt2 0 av dd pll2 v vco maximum oscillation frequency fmax 40 mhz vco minimum oscillation frequency fmin 15 (*1) mhz phase comparison frequency fref 17 mhz pll lock time tlock 10 15 ms ( * 1) when a clock with a frequency lower than 15mhz is required, for example 12.288mhz (= 32khz * 384, audio circuit operation clock at a sampling frequency of 32khz), this is generated by frequency dividing the clock by 2 as follows. 12.288mhz = 24.576mhz/2 10-bit ad converter characteristics at ta = 25 c, av dd adc = 3.3v, av ss adc = 0v ratings parameter symbol conditions min typ max unit pin adc power supply vavrh 2.7 3.6 v av dd adc adc ground voltage vavrl 0 v av ss adc analog input voltage van vavrl vavrh v an3-an0 adc resolution n 10 bit an3-an0 adc operation clock fc 16.5 mhz adc conversion frequency fs 1.04 mhz adc sample hold time twr 120 ns differential linearity error fdif neffect=10 1.5 lsb an3-an0 linearity error fln neffect=10 4.0 lsb an3-an0 zero-scale offset voltage (transit voltage from 0 to 1) vtz vavrl-0.1 vavrl vavrl+0.1 v an3-an0 full-scale offset voltage (transit voltage from 1022 to 1023) vtf vavrh-0.1 vavrh vavrh+0.1 v an3-an0 ladder stabilization time (*1) tstr after stby released 1 s reference resistor (*1) rr 770 power dissipation (*1) pd 15 mw ( * 1) all the characteristics are design values.
LC823410-10R no.a1696-6/23 usb interface characteristics at ta = -30 to +70 c, v dd 1=1.35 to 1.65v, av dd phy1=1.35 to 1.65v, av dd phy2=3.0 to 3.6v ratings parameter symbol conditions min typ max unit output pin impedance z hsdrv includes r s resistor 40.5 49.5 bus pull-up resistor on upstream forcing port r pu1 fs idle 0.900 1.575 k bus pull-up resistor on upstream forcing port r pu2 fs receiving or transmitting 1.425 3.090 k termination voltage for upstream forcing port pullup (full-speed) v term 3.15 3.45 v input levels for full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 v low-level input voltage v il 0.8 v differential input sensitivity v di |(d+)-(d-)| 0.2 v differential common mode range v cm includes v di range refer to figure 2.1 0.8 2.5 v output levels for full-speed: high-level output voltage v oh r l of 14.25k to v ss 2.8 3.6 v low-level output voltage v ol r l of 1.425k to 3.6v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs refer to figure 2.1 1.3 2.0 v input levels for high-speed: high-speed squelch detection threshold (differential signal) v hssq 100 150 mv high-speed data signaling common mode voltage range v hscm -50 +500 mv high-speed differential input signaling level refer to figure 2.2 output levels for high-speed: high-speed idle state v hsoi -10.0 +10 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol -10.0 +10 mv chirp j level (different signal) v chirpj 700 1100 mv chirp k level (different signal) v chirpk -900 -500 mv time to active-state: time from idle (standby/ suspend) state to active state (*) t act 1ms states identified by an asterisk ( * ) ? idle (standby/suspend) state: either one of the following 4 states: - either one of av dd phy1 and av dd phy2 is lower than the guaranteed operating voltage. - (usb register) devicecontrol: suspendsts=susp3endset=1 (usbphy suspended state) - (usb register) devicecontrol: rstphy=1 (usbphy reset state) - (syscon register) usbctl: shst by=1 (usbphy standby state) for details on the registers, see the lc823410-09c-e user?s manual (expansion module). ? active-state: any state in which the ic is not in any of the idle (standby/suspend) states.
LC823410-10R no.a1696-7/23 figure 2.1: differential input sensitivity range for full-speed figure 2.2: differential input sensitivity range for high-speed point1 level1 point2 point3 unit interval 0% 100% point4 point5 point6 level2 -400mv differential 0 volts differential +400mv differential -1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6 ? ? ? differential input voltage range differential output crossover voltage range ? ? ?
LC823410-10R no.a1696-8/23 ac characteristics: reset at ta = -30 to +70 c, v dd 1 = 1.05 to 1.65v, v dd 2 = 2.7 to 3.6v ratings parameter symbol conditions min typ max unit reset active time t resw 1 time after both of v dd 1 and v dd 2 reached within the allowable operation voltage range 10 s package dimensions unit : mm (typ) 3257a t resw 1 nres sanyo : tqfp120(14x14) 0.125 120 0.15 0.4 (1.2) 1 14.0 16.0 14.0 16.0 1.2max 0.1 (1.0) 0.5
LC823410-10R no.a1696-9/23 block diagram
LC823410-10R no.a1696-10/23 pin assignments i/o pin characteristics i input pin 3ic 3.3v cmos input 1ic 1.5v cmos input o output pin 3is 3.3v schmitt in put 1t3 1.5v 0.3ma tristate output b bi-directional pin 3icu 3.3v cmos input pullup x oscillation amplifier p power supply pin 3icd 3.3v cmos input pulldown 3a 3.3v analog 3isu 3.3v schmitt in put pullup 1a 1.5v analog 3o2 3.3v 2ma output 3t2 3.3v 2ma tristate output 3o6 3.3v 6ma output 3t6 3.3v 6ma tristate output no. name i/o characteristic function 1 test3 i 3is test pin (normally tied to low) 2 test4 i 3is test pin (normally tied to low) 3 test5 i 3is test pin (normally tied to low) 4 test6 i 3is test pin (normally tied to low) 5 tck i 3icu jtag test clock 6 rtck o 3o2 jtag test returned clock 7 ntrst i 3isu jtag test reset 8 tdi i 3icu jtag test data input 9 tms i 3icu jtag test mode select 10 tdo o 3o2 jtag test data output 11 nres i 3is reset input 12 phi(p11) b 3icu/3t2 ahb bus cloc k output/32.768khz clock output/gpio 13 extfiq(p2f) b 3isu/3t2 external fiq interrupt/gpio 14 sck0(p08) b 3isu/3t2 serial i/f 0 clock/gpio 15 sdo0(p09) b 3icu/3t2 serial i/f 0 output data/gpio 16 sdi0(p0a) b 3icu/3t2 serial i/f 0 input data/gpio 17 sck1(p14) b 3isu/3t2 serial i/f 1 clock/gpio 18 sdo1(p15) b 3icu/3t2 serial i/f 1 output data/gpio 19 sdi1(p16) b 3icu/3t2 serial i/f 1 input data/gpio 20 txd1(p2a) b 3icu/3t2 uart1 transmit data/gpio 21 rxd1(p2b) b 3icu/3t2 uart1 receive data/gpio 22 ti0ca0(p19) b 3icu/3t2 multiple time r input capture/output compare a0/gpio 23 ti0ca1(p1b) b 3icu/3t2 multiple time r input capture/output compare a1/gpio 24 v dd 1 p digital 1.5v power supply 25 v dd 2 p digital 3.3v power supply 26 v ss p digital ground 27 txd0(p1d) b 3icu/3t2 uart0 transmit data/gpio 28 rxd0(p1e) b 3icu/3t2 uart0 receive data/gpio 29 xfwe(p01) b 3icu/3t2 nand flash write enable 30 xfre(p02) b 3icu/3t2 nand flash read enable 31 xale(p03) b 3icu/3t2 nand flash address latch enable 32 xcle(p04) b 3icu/3t2 nand flash command latch enable 33 xfce1(p1f) b 3icu/3t2 nand flash chip enable 1/gpio 34 xfce0(p00) b 3icu/3t2 nand flash chip enable 0/gpio 35 xfwp(p05) b 3icu/3t2 nand flash write protect/gpio 36 xfbsy i 3is nand flash busy 37 fd0 b 3icd/3t2 nand flash data bit0 38 fd1 b 3icd/3t2 nand flash data bit1 39 v dd 2 p digital 3.3v power supply 40 v ss p digital ground continued on next page.
LC823410-10R no.a1696-11/23 continued from preceding page. no. i/o characteristic function 41 fd2 b 3icd/3t2 nand flash data bit2 42 fd3 b 3icd/3t2 nand flash data bit3 43 fd4 b 3icd/3t2 nand flash data bit4 44 fd5 b 3icd/3t2 nand flash data bit5 45 fd6 b 3icd/3t2 nand flash data bit6 46 fd7 b 3icd/3t4 nand flash data bit7 47 extint0(p21) b 3isu/3t2 external interrupt bit0/gpio 48 extint1(p22) b 3isu/3t2 external interrupt bit1/gpio 49 extint2(p23) b 3isu/3t2 external interrupt bit2/gpio 50 extint3(p24) b 3isu/3t2 external interrupt bit3/gpio 51 extint4(p25) b 3isu/3t2 external interrupt bit4/gpio 52 v dd 1 p digital 1.5v power supply 53 v dd 2 p digital 3.3v power supply 54 v ss p digital ground 55 dout o 3o2 pcm output data 56 din i 3icd pcm input data 57 bck b 3ic/3t2 pcm bit clock 58 lrlk(p12) b 3icu/3t2 pcm lr clock/gpio 59 mclk(p13) b 3icu/3t2 pcm main clock/gpio 60 scl(p28) b 3icu/3t2 i 2 c scl clock/gpio 61 sda(p29) b 3icu/3t2 i 2 c sda data/gpio 62 txd2(p2c) b 3icu/3t2 uart2 transmit data/gpio 63 rxd2(p2d) b 3icu/3t2 uart2 receive data/gpio 64 test1 i 3is test pin (normally tied to low) 65 test2 i 3is test pin (normally tied to low) 66 v dd 1 p digital 1.5v power supply 67 sdwp i 3ic sd card write protect 68 sdcd/ins i 3icu sd card detect/msins 69 sdcmd/bs b 3icu/3t6 sd card command/msbs 70 sdclk/sclk o 3o6 sd card clock/ms clock 71 sdat0/data0 b 3icud/3t6 sd card data/ms data 72 v ss p digital ground 73 v dd 3 p digital 3.3v/1.8v power supply 74 sdat1/data1 b 3icud/3t6 sd card data/ms data 75 sdat2/data2 b 3icud/3t6 sd card data/ms data 76 sdat3/data3 b 3icud/3t6 sd card data/ms data 77 av dd pll1 p pll1 analog power supply 78 av ss pll1 p pll1 analog ground 79 vcnt1 o 1a pll1 vco control 80 v dd xt p system /usb phy oscilla tion amplifier 1.5v power supply 81 v ss xt p system /usb phy oscillation amplifier ground 82 x in 1 i x system /usb phy os cillation amplifier input 83 x out 1 b x system /usb phy os cillation amplifier output 84 v dd rtc p rtc power supply 85 v ss rtc p rtc ground 86 xout32k o x rtc 32.768khz oscillation amplifier output 87 xin32k i x rtc 32.768khz os cillation amplifier input 88 vdet i 1ic voltage detect input 89 rtcint o 1t3 rtc interrupt output 90 backupb i 1ic rtc mode (r tc only or whole ic) 91 av dd phy1 p usb phy 1.5v power supply 92 av ss phy1 p usb phy analog ground continued on next page.
LC823410-10R no.a1696-12/23 continued from preceding page. no. i/o characteristic function 93 av ss phy1 p usb phy analog ground 94 rref b 3a usb phy reference resistor 95 av ss phy2 p usb phy analog ground 96 av dd phy2 p usb phy analog 3.3v power supply 97 av dd phy2 p usb phy analog 3.3v power supply 98 av ss phy2 p usb phy analog ground 99 av ss phy2 p usb phy analog ground 100 av ss phy2 p usb phy analog ground 101 av dd phy2 p usb phy analog 3.3v power supply 102 dp b 3a usb d+ 103 dm b 3a usb d- 104 av ss phy2 p usb phy analog ground 105 av dd phy2 p usb phy analog 3.3v power supply 106 av dd adc p a/d converter analog power supply 107 an0 i 3a a/d converter analog input ch0 108 an1 i 3a a/d converter analog input ch1 109 an2 i 3a a/d converter analog input ch2 110 an3 i 3a a/d converter analog input ch3 111 av ss adc p a/d converter analog ground 112 v ss p digital ground 113 x in 2 i x audio 16.9344mhz oscillator input 114 x out 2 o x audio 16.9344mhz oscillator output 115 v dd 1 p digital 1.5v power supply 116 av dd pll2 p pll2 analog power supply 117 av ss pll2 p pll2 analog ground 118 vcnt2 o 3a pll2 vco control 119 v dd 2 p digital 3.3v power supply 120 v ss p digital ground pin functions i input pin o output pin b bi-directional pin p power supply pin pin name direction count function (1) clock, reset, system pin (12 pins) test[6:1] i 6 test pin nres i 1 reset input x in 1 i 1 system/usb phy osc illator amplifier input x out 1 o 1 system/usb phy osc illator amplifier output x in 2 i 1 audio 16.9344mhz oscillator input x out 2 o 1 audio 16.9344mhz oscillator output phi(p11) o(b) 1 ahb bus clock output/32.768khz clock output functions as p11 after hard reset (2) interrupt (6 pins) extfiq(p2f) i(b) 1 external fiq interrupt functions as p2f after hard reset extint[4:0] (p[25:21]) i(b) 5 external interrupt functions as port after hard reset continued on next page.
LC823410-10R no.a1696-13/23 continued from preceding page. pin name direction count function (3) nand flash i/f (16 pins) xfceo(p00) o(b) 1 nand flash chip enable 0 functions as p00 after hard reset xfce1(p1f) o(b) 1 nand flash chip enable 1 functions as p1f after hard reset xfwe(p01) o(b) 1 nand flash write enable functions as p01 after hard reset xfre(p02) o(b) 1 nand flash read enable functions as p02 after hard reset xale(p03) o(b) 1 nand flash address latch enable functions as p03 after hard reset xcle(p04) o(b) 1 nand flash command latch enable functions as p04 after hard reset xfwp(p05) o(b) 1 nand flash write protect functions as p05 after hard reset xfbsy i 1 nand flash busy fd[7:0] b 8 nand flash data (4) sd card i/f, ms i/f (8 pins) sdwp0 i 1 sd card write protect sdcd0/ins i 1 sd card card detect / msins sdcmd0/bs b 1 sd card command / msbs sdclk0/sclk o 1 sd card clock / ms clock sdat0[3:0]/data[3:0] b 4 sd card data / ms data (5) pcm i/f (5 pins) dout o 1 pcm output data din i 1 pcm input data bck b 1 pcm bit clock lrck(p12) b(b) 1 pcm lr clock functions as lrck after hard reset mclk(p13) b(b) 1 pcm main clock functions as mclk after hard reset (6) serial i/f (14 pins) sck0 (p08) b 1 serial i/f 0 clock functions as p08 after hard reset sdo0 (p09) o (b) 1 serial i/f 0 output data functions as p09 after hard reset sdi0 (p0a) i (b) 1 serial i/f 0 input data functions as p0a after hard reset sck1 (p14) b (b) 1 serial i/f 1 clock functions as p14 after hard reset sdo1 (p15) o (b) 1 serial i/f 1 output data functions as p15 after hard reset sdi1 (p16) i (b) 1 serial i/f 1 input data functions as p16 after hard reset txd0 (p1d) o (b) 1 uart transmit data functions as p1d after hard reset rxd0 (p1e) i (b) 1 uart receive data functions as p1e after hard reset txd1 (p2a) o (b) 1 uart1 transmit data functions as p2a after hard reset rxd1 (p2b) i (b) 1 uart1 receive data functions as p2b after hard reset txd2(p2c) o (b) 1 uart2 transmit data functions as p2c after hard reset rxd2(p2d) i (b) 1 uart2 receive data functions as p2d after hard reset scl (p28) b (b) 1 i 2 c scl clock (open drain output) functions as p28 after hard reset sda (p29) b (b) 1 i 2 c sda data (open drain output) functions as p29 after hard reset continued on next page.
LC823410-10R no.a1696-14/23 continued from preceding page. pin name direction count function (7)timer (2 pins) tioca0 (p19) b(b) 1 multiple time r input capture/output compare a0 functions as p19 after hard reset tioca1 (p1b) b(b) 1 multiple time r input capture/output compare a1 functions as p1b after hard reset (8) jtag (6 pins) tck i 1 jtag test clock rtck o 1 jtag test returned clock ntrst i 1 jtag test reset tdi i 1 jtag test data input tms i 1 jtag test mode select tdo o 1 jtag test data output (9) rtc (5 pins) xout32k o 1 rtc 32.768khz os cillator amplifier output xin32k i 1 rtc 32.768khz os cillator amplifier input vdet i 1 voltage detect input rtcint o 1 rtc interrupt output backupb i 1 rtc mode (rtc only or lsi whole) (10) pll (2 pins) vcnt1 o 1 pll1 vco control vcnt2 o 1 pll2 vco control (11) usb (3 pins) dp b 1 usb d+ (device) dm b 1 usb d- (device) rref b 1 usb phy reference resistor (12) analog (4 pins) an[3:0] i 4 analog input (13) power supply pin (37 pins) v dd 1 p 4 digital 1.5v power supply v dd 2 p 4 digital 3.3v power supply v dd 3 p 1 digital 3.3v/1.8v power supply (s d card i/f, ms i/f power supply) v ss p 6 digital ground av dd pll1 p 1 pll1 analog power supply av ss pll1 p 1 pll1 analog ground av dd pll2 p 1 pll2 analog power supply av ss pll2 p 1 pll2 analog ground v dd rtc p 1 rtc power supply v ss rtc p 1 rtc ground v dd xt p 1 oscillation amplifier 1.5v power supply v ss xt p 1 oscillation amplifier ground av dd phy1 p 1 usb phy analog 1.5v power supply av ss phy1 p 2 usb phy analog ground av dd phy2 p 4 usb phy analog 3.3v power supply av ss phy2 p 5 usb phy analog ground av dd adc p 1 a/d converter analog power supply av ss adc p 1 a/d converter analog ground
LC823410-10R no.a1696-15/23 peripheral circuit example pll peripheral circuit 1 (for system) the pll1 circuit configuration is shown in the figure below. on the wiring board, connect the decoupling capacitors as close as possible to the pin, and separate the power line from other power supply lines to minimize noise. * c4: this is based on sanyo electric?s su rface mount device catalog (cv-bs series). note: generally, use r2 and c2 without mounting. however, if there is a problem that affects the pll ch aracteristics, the pll characteristics may be improved by mounting r2 and c2. therefore, be sure to prepare r2 and c2 wiring patterns beforehand. symbol value model or accuracy r1 100 to 200 5% r2 *m 5% c1 0.1 to 0.22 f c2 (approx. c1/100) c3 0.1 f capacitance error: 10% temperature characteristics: 10% (-25 to +85 c) c4 33 f 16cv33bs vcnt1 r1 c1 c2 av dd pll1 av ss pll1 av dd pll1 av ss pll1 + c4 c3 r2
LC823410-10R no.a1696-16/23 pll peripheral circuit 2 (for audio) the pll2 circuit configuration is shown in the figure below. on the wiring board, connect the decoupling capacitors as close as possible to the pins, and separate the power line from other power supply lines to minimize noise. * c4: this is based on sanyo electric?s surface mount device catalog (cv-bs series). note: generally, use r2 and c2 without mounting. however if there is a problem that affects the pll characteristics, the pl l characteristics may be improved by mounting r2 and c2. therefore, be sure to prepare r2 and c2 wiring patterns beforehand. reference for audio applications, experiments have confirmed that c1=1.0 f, c2=0.01 f can be effective in maximizing the jitte r reduction of the pll output clock. (note that this depends on the board and other environmental conditions, and the result is not guaranteed.) symbol value model or accuracy r1 100 to 200 5% r2 *m 5% c1 1.0 to 2.0 f c2 (approx. c1/100) c3 0.1 f capacitance error: 10% temperature characteristics: 10% (-25 to +85 c) c4 33 f 16cv33bs vcnt2 r1 c1 c2 av dd pll2 av ss pll2 av dd pll2 av ss pll2 + c4 c3 r2
LC823410-10R no.a1696-17/23 usb2.0 peripheral circuit be sure to always observe the items below when designing the circuit board. ? differential impedance control the dp/dm routing width, routing clear ance, and pcb layer spacing must be determined so that differential impedance of 90 can be achieved. we recommend a microstrip structure for realizing impedance matching. ? power supply (av dd phy2, av dd phy1) and ground (av ss phy2, av ss phy1) lines the separation of the power line and ground line only for usb usage is recommended. at a minimum, insert 10 f, 0.1 f, and 0.01 f capacitors between the power s upply and ground for filtering. to reject high-frequency noise, inserting the 0.01 f capacitor directly under the power pin and ground pin is recommended. note that 0.1 f capacitor is also effective for latch-up protection. ? crystal oscillator use a crystal oscillator connected to the x in 1 and x out 1 pins that has a fundamental wave of 12mhz, oscillation accuracy of 100p-pm or less, and place it near the ic. ? reference resistor connect the rref pin to the ground near the ic through the 680 (tolerance 1% or less) reference resistor. i 2 c peripheral circuit for the rs and rp values, see the i 2 c standards.
LC823410-10R no.a1696-18/23 xtal peripheral circuit xtal1 (12mhz) 12mhz oscillation amplifier rc reference values r1=1m , r2=0 , c1=c2=22pf applicable pins: x in 1, x out 1 xtal2 (16.9344mhz) 16.9344mhz oscillation amplifier rc reference values r1=1m , r2=0 , c1=c2=22pf applicable pins: x in 2, x out 2 xtalrtc (32.768khz) 32.768khz oscillation amplifier rc reference values r1=5.1m , r2=330k , c1=c2=22pf applicable pins: x in 32k, x out 32k (reference) oscillator product: dt-38 (daishinku corp.) c2 c1 r2 r1 c2 c1 r2 r1 c2 c1 r2 r1
LC823410-10R no.a1696-19/23 jtag pin treatment exam ples (both for use of ice and non-use of ice) ( * 1) the power-on reset is a reset signal that becomes activ e-low only when the power is turned on. set so that the ntrst pin is reset only by a reset from jtag and power-on reset. ( * 2) system reset includes a power-on reset and a reset sign al, requested by the system, that becomes active-low by a manual reset or other means. set so that the nres pin is reset by th e reset from jtag an d by system reset. see the data sheet for the nres pin reset specifications. th e ntrst pin has the same specifications as those of the nres pin. the power-on reset (open drain output) can be implemented, for example, by connecting it to the ground through a capacitor. the above configuration is a peripheral circuit example that assumes the use of a jtag ice by ydc (yokogawa digital computer) and can be applied both in cases where ice is and is not used. to use other products, inquire at the manufacturer. lc823410 tck v dd 2 tdi tms ntrst jtag connector rtck tdo 33 tck tdi tms ntrst rtck tdo power on reset (*1) (open drain output) nres nsrst system reset (*2) (open drain output) 10k
LC823410-10R no.a1696-20/23 jtag pin treatment exam ples (non-use of ice) ( * 1) system reset includes a power-on reset that becomes ac tive-low only when power is turned on, or a reset signal, requested by the system, that becomes activ e-low by a manual reset or other means. the ntrst pin has the same specifications as those of the nres pin, and at least a power-on reset must be implemented. as shown in this example, system reset can be connected to the nres pin directly. the above configuration is a simplified example of a pe ripheral circuit in the cas e that ice is not used. lc823410 tck tdi tms ntrst rtck tdo nres system reset (*1)
LC823410-10R no.a1696-21/23 power-on sequence * 1 the following relations must be satisfied. ? av dd phy2>=av dd adc v dd 2>=av dd pll2 v dd 2>=v dd 3 * 2 ? this is a period required only when the ahb clock is operating at a frequency higher than the internal operating frequency guaranteed by v dd 1>=1.35v, and this is needed for switching to an operating frequency guaranteed by v dd 1>=1.0v. the minimum time depends on the system. for the guaranteed operating frequency at each voltage, see the data sheet. (1) 3.3v *1 (v dd 2, v dd 3, av dd adc, av dd phy2, av dd pll2) (2)1.5v (v dd 1, v dd xt, av dd pll1, v dd rtc, av dd phy1) max 100ms 2.8v 1.1v 3.3v 1.5v min *2 3.0v 1.35v max 100ms usb power supply cutoff (s uch as cable disconnection) (when vbus = low is detected by at the ic pin)
LC823410-10R no.a1696-22/23 rtc pin power on/off control sequence when running rtc only at power-off of the device, it is required to detect the voltage drop of v dd 1, v dd 2 and set backupb to low. determine the detection level of v dd 1 and v dd 2 according to the conditions of the device. the vdet pin needs to be set to low when the rtc power s upply is cut off (when rtc operation is stopped). also, when drop in the rtc power supply voltage is detect ed, vdet must be set to low. the figure below shows the power on/off sequence when the detection level of v dd rtc is 0.9v or less. determine the detection level of v dd rtc according to the conditions of the device.
LC823410-10R no.a1696-23/23 (reference: internal control by backupb) sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides informati on as of june, 2010. specifications and information herein are subject to change without notice. ps

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